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Results:
1-7
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Results: 7
Authors:
Schurmann, B
Zimmermann, G
Citation: B. Schurmann et G. Zimmermann, Playout - A hierarchical layout system, VLSI DESIGN ENVIRONMENTS, 2000, pp. 1-58
Authors:
Stok, L
Citation: L. Stok, From network to artwork automatic schematic diagram generation, VLSI DESIGN ENVIRONMENTS, 2000, pp. 59-95
Authors:
Cyre, W
Citation: W. Cyre, Synthesis of digital systems from English specifications, VLSI DESIGN ENVIRONMENTS, 2000, pp. 96-143
Authors:
Simmons, WE
Lursinsap, C
Citation: We. Simmons et C. Lursinsap, Silicon cell compilers, VLSI DESIGN ENVIRONMENTS, 2000, pp. 144-185
Authors:
Lavagno, L
Villa, T
Sangiovanni-Vincentelli, AL
Citation: L. Lavagno et al., Advances in encoding for logic synthesis, VLSI DESIGN ENVIRONMENTS, 2000, pp. 186-216
Authors:
Eschermann, B
Citation: B. Eschermann, State assignment methods for synchronous sequential circuits, VLSI DESIGN ENVIRONMENTS, 2000, pp. 217-264
Authors:
Vander Zanden, N
Gajski, D
Citation: N. Vander Zanden et D. Gajski, MILO: A microarchitecture and logic optimization system, VLSI DESIGN ENVIRONMENTS, 2000, pp. 265-299
Risultati:
1-7
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