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Results:
1-16
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Results: 16
Authors:
Wollowski, R
Beister, J
Citation: R. Wollowski et J. Beister, Comprehensive causal specification of asynchronous controller and arbiter behaviour - A generalized signal transition graph, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 3-32
Authors:
Xia, F
Clark, I
Citation: F. Xia et I. Clark, Complementing role models with Petri nets in studying asynchronous data communications, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 33-49
Authors:
Schaefer, DH
Sosa, JA
Citation: Dh. Schaefer et Ja. Sosa, Petri net representations of computational and communication operators, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 51-74
Authors:
Schwiegelshohn, U
Thiele, L
Citation: U. Schwiegelshohn et L. Thiele, Properties of change diagrams, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 77-92
Authors:
Meyer, R
Thiagarajan, PS
Citation: R. Meyer et Ps. Thiagarajan, LTRL-based model checking for a restricted class of signal transition graphs, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 93-106
Authors:
Kovalyov, A
Citation: A. Kovalyov, A polynomial algorithm to compute the concurrency relation of a regular STG, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 107-126
Authors:
Marranghello, N
Mirkowski, J
Bilinski, K
Citation: N. Marranghello et al., Synthesis of synchronous digital systems specified by Petri nets, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 129-150
Authors:
Blunno, I
Lavagno, L
Citation: I. Blunno et L. Lavagno, Deriving Signal Transition Graphs from behavioral Verilog HDL, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 151-170
Authors:
Chung, SH
Furber, S
Citation: Sh. Chung et S. Furber, The design of the control circuits for an asynchronous instruction prefetch unit using signal transition graphs - An asynchronous instruction prefetch unit design, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 171-190
Authors:
Rokyta, P
Fengler, W
Hummel, T
Citation: P. Rokyta et al., Electronic system design automation using high level Petri nets, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 193-204
Authors:
Machado, RJ
Fernandes, JM
Esteves, AJ
Santos, HD
Citation: Rj. Machado et al., An evolutionary approach to the use of Petri Net based models - From parallel controllers to HW/SW codesign, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 205-222
Authors:
Prothero, D
Citation: D. Prothero, Modelling and implementation of Petri nets using VHDL, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 223-236
Authors:
Xie, AG
Beerel, PA
Citation: Ag. Xie et Pa. Beerel, Performance analysis of asynchronous circuits and systems using stochastictimed Petri nets, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 239-268
Authors:
Witlox, BRTM
van der Wolf, P
Aarts, EHL
van der Aalst, WMP
Citation: Brtm. Witlox et al., Performance analysis of dataflow architectures using timed coloured Petri nets, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 269-289
Authors:
Gries, M
Citation: M. Gries, Modeling a memory subsystem with Petri nets: A case study, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 291-310
Authors:
Zuberek, WM
Citation: Wm. Zuberek, Performance modeling of multithreaded distributed memory architectures, HARDWARE DESIGN AND PETRI NETS, 2000, pp. 311-331
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