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Results:
1-9
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Table of contents of journal:
Results: 9
Automated design synthesis and partitioning for adaptive reconfigurable hardware
Authors:
Vemuri, R Govindarajan, S Ouaiss, I Kaul, M Srinivasan, V Radhakrishnan, S Sundaraman, S Ganesan, S Pandey, A Lakshmikanthan, P
Citation:
R. Vemuri et al., Automated design synthesis and partitioning for adaptive reconfigurable hardware, STUD FUZZ S, 74, 2001, pp. 3-52
High-performance hardware design and implementation of genetic algorithms
Authors:
Shackleford, B Okushi, E Yasuda, M Koizumi, H Seo, K Iwamoto, T Yasuura, H
Citation:
B. Shackleford et al., High-performance hardware design and implementation of genetic algorithms, STUD FUZZ S, 74, 2001, pp. 53-87
Hardware implementation of intelligent systems
Authors:
Russo, M Caponetto, L
Citation:
M. Russo et L. Caponetto, Hardware implementation of intelligent systems, STUD FUZZ S, 74, 2001, pp. 91-120
High performance fuzzy processors
Authors:
Cardarilli, GC Lojacono, R Re, M
Citation:
Gc. Cardarilli et al., High performance fuzzy processors, STUD FUZZ S, 74, 2001, pp. 121-146
A digital fuzzy processor for fuzzy-rule-based systems
Authors:
Falchieri, D Gabrielli, A Gandolfi, E
Citation:
D. Falchieri et al., A digital fuzzy processor for fuzzy-rule-based systems, STUD FUZZ S, 74, 2001, pp. 147-164
Optimum multiuser detection for CDMA systems using the Mean Field Annealing neural network
Authors:
Chang, PR Wang, BC Tan, TH
Citation:
Pr. Chang et al., Optimum multiuser detection for CDMA systems using the Mean Field Annealing neural network, STUD FUZZ S, 74, 2001, pp. 167-192
Analog VLSI hardware implementation of a supervised learning algorithm
Authors:
Bo, GM Caviglia, D Chible, H Valle, M
Citation:
Gm. Bo et al., Analog VLSI hardware implementation of a supervised learning algorithm, STUD FUZZ S, 74, 2001, pp. 193-217
pRAM: The probabilistic RAM neural processor
Authors:
Clarkson, TG
Citation:
Tg. Clarkson, pRAM: The probabilistic RAM neural processor, STUD FUZZ S, 74, 2001, pp. 219-241
Parallel subgraph matching on a hierarchical interconnection network
Authors:
Campbell, S Kumar, M Bunke, H
Citation:
S. Campbell et al., Parallel subgraph matching on a hierarchical interconnection network, STUD FUZZ S, 74, 2001, pp. 245-275
Risultati:
1-9
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