Citation: Cj. Alpert et al., MULTILEVEL CIRCUIT PARTITIONING, IEEE transactions on computer-aided design of integrated circuits and systems, 17(8), 1998, pp. 655-667
Authors:
ALPERT CJ
CHAN TF
KAHNG AB
MARKOV IL
MULET P
Citation: Cj. Alpert et al., FASTER MINIMIZATION OF LINEAR WIRELENGTH FOR GLOBAL PLACEMENT, IEEE transactions on computer-aided design of integrated circuits and systems, 17(1), 1998, pp. 3-13
Citation: Cj. Alpert et Ab. Kahng, A GENERAL FRAMEWORK FOR VERTEX ORDERINGS WITH APPLICATIONS TO CIRCUITCLUSTERING, IEEE transactions on very large scale integration (VLSI) systems, 4(2), 1996, pp. 240-246
Authors:
ALPERT CJ
HU TC
HUANG JH
KAHNG AB
KARGER D
Citation: Cj. Alpert et al., PRIM-DIJKSTRA TRADEOFFS FOR IMPROVED PERFORMANCE-DRIVEN ROUTING TREE DESIGN, IEEE transactions on computer-aided design of integrated circuits and systems, 14(7), 1995, pp. 890-896
Citation: Cj. Alpert et Ab. Kahng, MULTIWAY PARTITIONING VIA GEOMETRIC EMBEDDINGS, ORDERINGS, AND DYNAMIC-PROGRAMMING, IEEE transactions on computer-aided design of integrated circuits and systems, 14(11), 1995, pp. 1342-1358