Authors: Belluomini, W Myers, CJ Hofstee, HP

Citation: W. Belluomini et al., Timed circuit verification using TEL structures, IEEE COMP A, 20(1), 2001, pp. 129-146

Authors: Belluomini, W Myers, CJ

Citation: W. Belluomini et Cj. Myers, Timed state space exploration using POSET's, IEEE COMP A, 19(5), 2000, pp. 501-520