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Results: 1-11 |
Results: 11
CIRCUIT RETIMING APPLIED TO DECOMPOSED SOFTWARE PIPELINING
Authors: CALLAND PY DARTE A ROBERT Y
Citation: Py. Calland et al., CIRCUIT RETIMING APPLIED TO DECOMPOSED SOFTWARE PIPELINING, IEEE transactions on parallel and distributed systems, 9(1), 1998, pp. 24-35
ON THE REMOVAL OF ANTI-DEPENDENCES AND OUTPUT-DEPENDENCES
Authors: CALLAND PY DARTE A ROBERT Y VIVIEN F
Citation: Py. Calland et al., ON THE REMOVAL OF ANTI-DEPENDENCES AND OUTPUT-DEPENDENCES, International journal of parallel programming, 26(3), 1998, pp. 285-312
LOOP PARALLELIZATION ALGORITHMS - FROM PARALLELISM EXTRACTION TO CODE
Authors: BOULET P DARTE A SILBER GA VIVIEN F
Citation: P. Boulet et al., LOOP PARALLELIZATION ALGORITHMS - FROM PARALLELISM EXTRACTION TO CODE, Parallel computing, 24(3-4), 1998, pp. 421-444
OPTIMAL FINE AND MEDIUM GRAIN PARALLELISM DETECTION IN POLYHEDRAL REDUCED DEPENDENCE GRAPHS
Authors: DARTE A VIVIEN F
Citation: A. Darte et F. Vivien, OPTIMAL FINE AND MEDIUM GRAIN PARALLELISM DETECTION IN POLYHEDRAL REDUCED DEPENDENCE GRAPHS, International journal of parallel programming, 25(6), 1997, pp. 447-496
HPFIT, A SET OF INTEGRATED TOOLS FOR THE PARALLELIZATION OF APPLICATIONS USING HIGH-PERFORMANCE FORTRAN .1. HPFIT AND THE TRANSTOOL ENVIRONMENT
Authors: BRANDES T CHAUMETTE S COUNILH MC ROMAN J DARTE A DESPREZ F MIGNOT JC
Citation: T. Brandes et al., HPFIT, A SET OF INTEGRATED TOOLS FOR THE PARALLELIZATION OF APPLICATIONS USING HIGH-PERFORMANCE FORTRAN .1. HPFIT AND THE TRANSTOOL ENVIRONMENT, Parallel computing, 23(1-2), 1997, pp. 71-87
PLUGGING ANTI AND OUTPUT DEPENDENCE REMOVAL TECHNIQUES INTO LOOP PARALLELIZATION ALGORITHM
Authors: CALLAND PY DARTE A ROBERT Y VIVIEN F
Citation: Py. Calland et al., PLUGGING ANTI AND OUTPUT DEPENDENCE REMOVAL TECHNIQUES INTO LOOP PARALLELIZATION ALGORITHM, Parallel computing, 23(1-2), 1997, pp. 251-266
EVALUATING ARRAY EXPRESSIONS ON MASSIVELY-PARALLEL MACHINES WITH COMMUNICATION COMPUTATION OVERLAP/
Authors: BOUCHITTE V BOULET P DARTE A ROBERT Y
Citation: V. Bouchitte et al., EVALUATING ARRAY EXPRESSIONS ON MASSIVELY-PARALLEL MACHINES WITH COMMUNICATION COMPUTATION OVERLAP/, The international journal of supercomputer applications and high performance computing, 9(3), 1995, pp. 205-219
AFFINE-BY-STATEMENT SCHEDULING OF UNIFORM AND AFFINE LOOP NESTS OVER PARAMETRIC DOMAINS
Authors: DARTE A ROBERT Y
Citation: A. Darte et Y. Robert, AFFINE-BY-STATEMENT SCHEDULING OF UNIFORM AND AFFINE LOOP NESTS OVER PARAMETRIC DOMAINS, Journal of parallel and distributed computing, 29(1), 1995, pp. 43-59
CONSTRUCTIVE METHODS FOR SCHEDULING UNIFORM LOOP NESTS
Authors: DARTE A ROBERT Y
Citation: A. Darte et Y. Robert, CONSTRUCTIVE METHODS FOR SCHEDULING UNIFORM LOOP NESTS, IEEE transactions on parallel and distributed systems, 5(8), 1994, pp. 814-822
(PEN)-ULTIMATE TILING
Authors: BOULET P DARTE A RISSET T ROBERT Y
Citation: P. Boulet et al., (PEN)-ULTIMATE TILING, Integration, 17(1), 1994, pp. 33-51
MAPPING UNIFORM LOOP NESTS ONTO DISTRIBUTED-MEMORY ARCHITECTURES
Authors: DARTE A ROBERT Y
Citation: A. Darte et Y. Robert, MAPPING UNIFORM LOOP NESTS ONTO DISTRIBUTED-MEMORY ARCHITECTURES, Parallel computing, 20(5), 1994, pp. 679-710
Risultati: 1-11 |