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Results: 3
Analysis of the impact of process variations on clock skew
Authors:
Zanella, S Nardi, A Neviani, A Quarantelli, M Saxena, S Guardiani, C
Citation:
S. Zanella et al., Analysis of the impact of process variations on clock skew, IEEE SEMIC, 13(4), 2000, pp. 401-407
Untitled
Authors:
Guardiani, C Milor, L
Citation:
C. Guardiani et L. Milor, Untitled, IEEE SEMIC, 12(4), 1999, pp. 385-385
Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
Authors:
Nardi, A Neviani, A Zanoni, E Quarantelli, M Guardiani, C
Citation:
A. Nardi et al., Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies, IEEE SEMIC, 12(4), 1999, pp. 396-402
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