Authors:
SUGAWARA H
TAKESHIMA T
TAKADA H
HISAMUNE YS
KANAMORI K
OKAZAWA T
MUROTANO T
SASAKI I
Citation: H. Sugawara et al., DESIGN OF A 3.3 V SINGLE POWER-SUPPLY 64 MBIT FLASH MEMORY WITH DYNAMIC BIT-LINE LATCH (DBL) PROGRAMMING SCHEME, IEICE transactions on electronics, E78C(7), 1995, pp. 825-831
Authors:
KANAMORI K
HISAMUNE YS
KUBOTA T
HASEGAWA E
ISHITANI A
OKAZAWA T
Citation: K. Kanamori et al., A HIGH CAPACITIVE COUPLING RATIO (HICR) CELL FOR SINGLE 3V POWER-SUPPLY FLASH MEMORIES, NEC research & development, 36(1), 1995, pp. 122-131
Authors:
KANAMORI K
HISAMUNE YS
KUBOTA T
SUZUKI Y
TSUKIJI M
HASEGAWA E
ISHITANI A
OKAZAWA T
Citation: K. Kanamori et al., A HIGH CAPACITIVE COUPLING RATIO (HICR) CELL FOR SINGLE 3 VOLT POWER-SUPPLY FLASH MEMORIES, IEICE transactions on electronics, E77C(8), 1994, pp. 1296-1302