Authors: Noda, K Takeda, K Matsui, K Ito, S Masuoka, S Kawamoto, H Ikezawa, N Aimoto, Y Nakamura, N Iwasaki, T Toyoshima, H Horiuchi, T

Citation: K. Noda et al., An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield, IEEE J SOLI, 36(3), 2001, pp. 510-515