ACNP - Italian Periodicals Catalogue

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Results: 1-25 | 26-50 | 51-75 | 76-88

Results: 51-75/88

Programmable SOCs provide slick designs

Authors: Lipman, J

Citation: J. Lipman, Programmable SOCs provide slick designs, EDN, 44(21), 1999, pp. 16-16

Tool aids analog-filter design

Authors: Lipman, J

Citation: J. Lipman, Tool aids analog-filter design, EDN, 44(21), 1999, pp. 24-24

Chip-core protection: everybody's business

Authors: Lipman, J

Citation: J. Lipman, Chip-core protection: everybody's business, EDN, 44(21), 1999, pp. 99

FPGA functional verification gets a speed boost

Authors: Lipman, J

Citation: J. Lipman, FPGA functional verification gets a speed boost, EDN, 44(20), 1999, pp. 26-26

New tools help you "C" the light for hardware design

Authors: Lipman, J

Citation: J. Lipman, New tools help you "C" the light for hardware design, EDN, 44(20), 1999, pp. 26-26

Flash! Foundry migrates logic/memory process to 0.35 mu m

Authors: Lipman, J

Citation: J. Lipman, Flash! Foundry migrates logic/memory process to 0.35 mu m, EDN, 44(2), 1999, pp. 22-22

Rate ATE compatibility at chip simulation

Authors: Lipman, J

Citation: J. Lipman, Rate ATE compatibility at chip simulation, EDN, 44(19), 1999, pp. 28-28

Improved standard broadens chip-modeling capability

Authors: Lipman, J

Citation: J. Lipman, Improved standard broadens chip-modeling capability, EDN, 44(19), 1999, pp. 28-28

Design suite accelerates SOC development

Authors: Lipman, J

Citation: J. Lipman, Design suite accelerates SOC development, EDN, 44(19), 1999, pp. 30-30

Memory-compiler redundancy boosts yield

Authors: Lipman, J

Citation: J. Lipman, Memory-compiler redundancy boosts yield, EDN, 44(18), 1999, pp. 22-22

The price is not quite right

Authors: Lipman, J

Citation: J. Lipman, The price is not quite right, EDN, 44(18), 1999, pp. 44-44

System-level software opens doors

Authors: Lipman, J

Citation: J. Lipman, System-level software opens doors, EDN, 44(17), 1999, pp. 26-26

RTL tools take design planning to a higher level

Authors: Lipman, J

Citation: J. Lipman, RTL tools take design planning to a higher level, EDN, 44(16), 1999, pp. 87

Chip synthesis, place and route unite

Authors: Lipman, J

Citation: J. Lipman, Chip synthesis, place and route unite, EDN, 44(15), 1999, pp. 16-16

Mixed-signal simulator speeds past Spice

Authors: Lipman, J

Citation: J. Lipman, Mixed-signal simulator speeds past Spice, EDN, 44(15), 1999, pp. 18-18

All-in-one board place-and-route tools emerge

Authors: Lipman, J

Citation: J. Lipman, All-in-one board place-and-route tools emerge, EDN, 44(15), 1999, pp. 20-20

Cadence to buy OrCAD

Authors: Lipman, J

Citation: J. Lipman, Cadence to buy OrCAD, EDN, 44(14), 1999, pp. 16-16

Reality check: Copper interconnect enables fast chips

Authors: Lipman, J

Citation: J. Lipman, Reality check: Copper interconnect enables fast chips, EDN, 44(14), 1999, pp. 18-18

Chip-level software fuels clock-tree and power-grid design

Authors: Lipman, J

Citation: J. Lipman, Chip-level software fuels clock-tree and power-grid design, EDN, 44(14), 1999, pp. 20-20

Tool suite weds emulation, simulation

Authors: Lipman, J

Citation: J. Lipman, Tool suite weds emulation, simulation, EDN, 44(14), 1999, pp. 22-22

Tool helps you floorplan chips

Authors: Lipman, J

Citation: J. Lipman, Tool helps you floorplan chips, EDN, 44(13), 1999, pp. 14-14

EDA vendor gets physical with new chip router

Authors: Lipman, J

Citation: J. Lipman, EDA vendor gets physical with new chip router, EDN, 44(13), 1999, pp. 20-20

Tools aid cell-library analysis

Authors: Lipman, J

Citation: J. Lipman, Tools aid cell-library analysis, EDN, 44(13), 1999, pp. 22-22

DAC's back with jazzy new design tools

Authors: Lipman, J

Citation: J. Lipman, DAC's back with jazzy new design tools, EDN, 44(12), 1999, pp. 16

Synthesis vendor gets physical with verification

Authors: Lipman, J

Citation: J. Lipman, Synthesis vendor gets physical with verification, EDN, 44(11), 1999, pp. 16-16

Risultati: 1-25 | 26-50 | 51-75 | 76-88