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Results: 1-9 |
Results: 9
OPERATIONAL AND TEST-PERFORMANCE IN THE PRESENCE OF BUILT-IN CURRENT SENSORS
Authors: MENON SM MALAIYA YK JAYASUMANA AP TONG CQ
Citation: Sm. Menon et al., OPERATIONAL AND TEST-PERFORMANCE IN THE PRESENCE OF BUILT-IN CURRENT SENSORS, VLSI design, 5(3), 1997, pp. 285-298
ECL STORAGE ELEMENTS - MODELING OF FAULTY BEHAVIOR
Authors: MENON SM MALAIYA YK JAYASUMANA AP
Citation: Sm. Menon et al., ECL STORAGE ELEMENTS - MODELING OF FAULTY BEHAVIOR, IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 44(11), 1997, pp. 970-974
BICMOS DOMINO - A NOVEL HIGH-SPEED DYNAMIC BICMOS LOGIC
Authors: MENON SM JAYASUMANA AP MALAIYA YK
Citation: Sm. Menon et al., BICMOS DOMINO - A NOVEL HIGH-SPEED DYNAMIC BICMOS LOGIC, International journal of electronics, 83(2), 1997, pp. 177-189
FAULT MODELING OF ECL FOR HIGH FAULT COVERAGE OF PHYSICAL DEFECTS
Authors: MENON SM MALAIYA YK JAYASUMANA AP
Citation: Sm. Menon et al., FAULT MODELING OF ECL FOR HIGH FAULT COVERAGE OF PHYSICAL DEFECTS, VLSI design, 4(3), 1996, pp. 231-242
MANIFESTATIONS OF FAULTS IN SINGLE-BJT AND DOUBLE-BJT BICMOS LOGIC GATES
Authors: MENON SM JAYASUMANA AP MALAIYA YK
Citation: Sm. Menon et al., MANIFESTATIONS OF FAULTS IN SINGLE-BJT AND DOUBLE-BJT BICMOS LOGIC GATES, IEE proceedings. Computers and digital techniques, 142(2), 1995, pp. 135-144
TESTABLE DESIGN OF BICMOS CIRCUITS FOR STUCK-OPEN FAULT-DETECTION USING SINGLE PATTERNS
Authors: MENON SM MALAIYA YK JAYASUMANA AP RAJSUMAN R
Citation: Sm. Menon et al., TESTABLE DESIGN OF BICMOS CIRCUITS FOR STUCK-OPEN FAULT-DETECTION USING SINGLE PATTERNS, IEEE journal of solid-state circuits, 30(8), 1995, pp. 855-863
DATA-FEEDTHROUGH FAULTS IN CIRCUITS USING UNCLOCKED STORAGE ELEMENTS
Authors: ALASSADI WK LU D JAYASUMANA AP MALAIYA YK TONG CQ
Citation: Wk. Alassadi et al., DATA-FEEDTHROUGH FAULTS IN CIRCUITS USING UNCLOCKED STORAGE ELEMENTS, Electronics Letters, 30(10), 1994, pp. 764-765
MODELING AND ANALYSIS OF BRIDGING FAULTS IN EMITTER-COUPLED LOGIC (ECL) CIRCUITS
Authors: MENON SM JAYASUMANA AP MALAIYA YK CLINKINBEARD DR
Citation: Sm. Menon et al., MODELING AND ANALYSIS OF BRIDGING FAULTS IN EMITTER-COUPLED LOGIC (ECL) CIRCUITS, IEE proceedings. Part E. Computers and digital techniques, 140(4), 1993, pp. 220-226
AN EXAMINATION OF FAULT EXPOSURE RATIO
Authors: MALAIYA YK VONMAYRHAUSER A SRIMANI PK
Citation: Yk. Malaiya et al., AN EXAMINATION OF FAULT EXPOSURE RATIO, IEEE transactions on software engineering, 19(11), 1993, pp. 1087-1094
Risultati: 1-9 |