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Citation: At. Ishii et al., OPTIMIZING 2-PHASE, LEVEL-CLOCKED CIRCUITRY, Journal of the ACM, 44(1), 1997, pp. 148-199

Authors: KNAPP MC KINDLMANN PJ PAPAEFTHYMIOU MC

Citation: Mc. Knapp et al., DESIGN AND EVALUATION OF ADIABATIC ARITHMETIC UNITS, Analog integrated circuits and signal processing, 14(1-2), 1997, pp. 71-79

Authors: LALGUDI KN PAPAEFTHYMIOU MC

Citation: Kn. Lalgudi et Mc. Papaefthymiou, RETIMING EDGE-TRIGGERED CIRCUITS UNDER GENERAL DELAY MODELS, IEEE transactions on computer-aided design of integrated circuits and systems, 16(12), 1997, pp. 1393-1408

Authors: LALGUDI KN PAPAEFTHYMIOU MC

Citation: Kn. Lalgudi et Mc. Papaefthymiou, COMPUTING STRICTLY-SECOND SHORTEST PATHS, Information processing letters, 63(4), 1997, pp. 177-181

Authors: PAPAEFTHYMIOU MC

Citation: Mc. Papaefthymiou, UNDERSTANDING RETIMING THROUGH MAXIMUM AVERAGE-DELAY CYCLES, Mathematical systems theory, 27(1), 1994, pp. 65-84