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Citation: Y. Liu et al., ftd: Frequency to time domain conversion for reduced-order interconnect simulation, IEEE CIRC-I, 48(4), 2001, pp. 500-506

Authors: Celik, M Pileggi, LT

Citation: M. Celik et Lt. Pileggi, Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees, IEEE COMP A, 18(3), 1999, pp. 293-300

Authors: Beattie, MW Pileggi, LT

Citation: Mw. Beattie et Lt. Pileggi, Error bounds for capacitance extraction via window techniques, IEEE COMP A, 18(3), 1999, pp. 311-321