Authors: Paul, D Chatterjee, M Pradhan, DK

Citation: D. Paul et al., VERILAT: Verification using logic augmentation and transformations, IEEE COMP A, 19(9), 2000, pp. 1041-1051

Authors: Chatterjee, M Banerjee, S Pradhan, DK

Citation: M. Chatterjee et al., Buffer assignment algorithms on data driven ASICs, IEEE COMPUT, 49(1), 2000, pp. 16-32

Authors: Pradhan, DK Chatterjee, M

Citation: Dk. Pradhan et M. Chatterjee, GLFSR - A new test pattern generator for built-in-self-test, IEEE COMP A, 18(2), 1999, pp. 238-247