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Citation: G. Even et al., RETIMING REVISITED AND REVERSED, IEEE transactions on computer-aided design of integrated circuits and systems, 15(3), 1996, pp. 348-357

Authors: SILBERMAN GM SPILLINGER IY

Citation: Gm. Silberman et Iy. Spillinger, A BACKTRACING-ORIENTED PROCEDURE FOR THE ANALYSIS OF COMBINATIONAL GATE-LEVEL DESIGNS, Integration, 17(3), 1994, pp. 271-286

Authors: INTRATER GD SPILLINGER IY

Citation: Gd. Intrater et Iy. Spillinger, PERFORMANCE EVALUATION OF A DECODED INSTRUCTION CACHE FOR VARIABLE INSTRUCTION LENGTH COMPUTERS, I.E.E.E. transactions on computers, 43(10), 1994, pp. 1140-1150

Authors: WEISS S SPILLINGER IY SILBERMAN GM

Citation: S. Weiss et al., ARCHITECTURAL IMPROVEMENTS FOR A DATA-DRIVEN VLSI PROCESSING ARRAY, Journal of parallel and distributed computing, 19(4), 1993, pp. 308-322