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Results: 1-14 |
Results: 14
400-MHZ RANDOM COLUMN OPERATING SDRAM TECHNIQUES WITH SELF-SKEW COMPENSATION
Authors: HAMAMOTO T TSUKUDE M ARIMOTO K KONISHI Y MIYAMOTO T OZAKI H YAMADA M
Citation: T. Hamamoto et al., 400-MHZ RANDOM COLUMN OPERATING SDRAM TECHNIQUES WITH SELF-SKEW COMPENSATION, IEEE journal of solid-state circuits, 33(5), 1998, pp. 770-778
A LONG DATA RETENTION SOI DRAM WITH THE BODY REFRESH FUNCTION
Authors: TOMISHIMA S MORISHITA F TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Tomishima et al., A LONG DATA RETENTION SOI DRAM WITH THE BODY REFRESH FUNCTION, IEICE transactions on electronics, E80C(7), 1997, pp. 899-904
HIGH-SPEED HIGH-BANDWIDTH DESIGN METHODOLOGIES FOR ON-CHIP DRAM CORE MULTIMEDIA SYSTEM LSIS/
Authors: TSURUDA T KOBAYASHI M TSUKUDE M YAMAGATA T ARIMOTO K YAMADA M
Citation: T. Tsuruda et al., HIGH-SPEED HIGH-BANDWIDTH DESIGN METHODOLOGIES FOR ON-CHIP DRAM CORE MULTIMEDIA SYSTEM LSIS/, IEEE journal of solid-state circuits, 32(3), 1997, pp. 477-482
A 1.2 TO 3.3-V WIDE VOLTAGE-RANGE LOW-POWER DRAM WITH A CHARGE-TRANSFER PRESENSING SCHEME/
Authors: TSUKUDE M KUGE S FUJINO T ARIMOTO K
Citation: M. Tsukude et al., A 1.2 TO 3.3-V WIDE VOLTAGE-RANGE LOW-POWER DRAM WITH A CHARGE-TRANSFER PRESENSING SCHEME/, IEEE journal of solid-state circuits, 32(11), 1997, pp. 1721-1727
SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES
Authors: KUGE S MORISHITA F TSURUDA T TOMISHIMA S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Kuge et al., SOI-DRAM CIRCUIT TECHNOLOGIES FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES, IEICE transactions on electronics, E79C(7), 1996, pp. 997-1002
A BLANKET SOURCE LINE ARCHITECTURE WITH TRIPLE METAL FOR GIGA SCALE MEMORY LSIS
Authors: TOMISHIMA S KUGE S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Tomishima et al., A BLANKET SOURCE LINE ARCHITECTURE WITH TRIPLE METAL FOR GIGA SCALE MEMORY LSIS, IEICE transactions on electronics, E79C(6), 1996, pp. 808-811
SOI-DRAM CIRCUIT TECHNOLOGIES - FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES
Authors: KUGE S MORISHITA F TSURUDA T TOMISHIMA S TSUKUDE M YAMAGATA T ARIMOTO K
Citation: S. Kuge et al., SOI-DRAM CIRCUIT TECHNOLOGIES - FOR LOW-POWER HIGH-SPEED MULTIGIGA SCALE MEMORIES, IEEE journal of solid-state circuits, 31(4), 1996, pp. 586-591
A 1.6-GB S DATA-RATE 1-GB SYNCHRONOUS DRAM WITH HIERARCHICAL SQUARE-SHAPED MEMORY BLOCK AND DISTRIBUTED BANK ARCHITECTURE/
Authors: SAKASHITA N NITTA Y SHIMOMURA K OKUDA F SHIMANO H YAMAKAWA S TSUKUDE M ARIMOTO K BABA S KOMORI S KYUMA K YASUOKA A ABE H
Citation: N. Sakashita et al., A 1.6-GB S DATA-RATE 1-GB SYNCHRONOUS DRAM WITH HIERARCHICAL SQUARE-SHAPED MEMORY BLOCK AND DISTRIBUTED BANK ARCHITECTURE/, IEEE journal of solid-state circuits, 31(11), 1996, pp. 1645-1655
LOW-VOLTAGE CIRCUIT-DESIGN TECHNIQUES FOR BATTERY-OPERATED AND OR GIGA-SCALE DRAMS/
Authors: YAMAGATA T TOMISHIMA S TSUKUDE M TSURUDA T HASHIZUME Y ARIMOTO K
Citation: T. Yamagata et al., LOW-VOLTAGE CIRCUIT-DESIGN TECHNIQUES FOR BATTERY-OPERATED AND OR GIGA-SCALE DRAMS/, IEEE journal of solid-state circuits, 30(11), 1995, pp. 1183-1188
AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME
Authors: ASAKURA M OOISHI T TSUKUDE M TOMISHIMA S EIMORI T HIDAKA H OHNO Y ARIMOTO K FUJISHIMA K NISHIMURA T YOSHIHARA T
Citation: M. Asakura et al., AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1303-1309
AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME
Authors: ASAKURA M OOISHI T TSUKUDE M TOMISHIMA S EIMORI T HIDAKA H OHNO Y ARIMOTO K FUJISHIMA K NISHIMURA T YOSHIHARA T
Citation: M. Asakura et al., AN EXPERIMENTAL 256-MB DRAM WITH BOOSTED SENSE-GROUND SCHEME, IEEE journal of solid-state circuits, 29(11), 1994, pp. 1303-1309
A SMART DESIGN METHODOLOGY WITH DISTRIBUTED EXTRA GATE-ARRAYS FOR ADVANCED ULSI MEMORIES
Authors: TSUKUDE M ARIMOTO K ASAKURA M HIDAKA H FUJISHIMA K
Citation: M. Tsukude et al., A SMART DESIGN METHODOLOGY WITH DISTRIBUTED EXTRA GATE-ARRAYS FOR ADVANCED ULSI MEMORIES, IEICE transactions on electronics, E76C(11), 1993, pp. 1589-1594
A LINE-MODE TEST WITH DATA REGISTER FOR ULSI MEMORY ARCHITECTURE
Authors: OOISHI T TSUKUDE M ARIMOTO K MATSUDA Y FUJISHIMA K
Citation: T. Ooishi et al., A LINE-MODE TEST WITH DATA REGISTER FOR ULSI MEMORY ARCHITECTURE, IEICE transactions on electronics, E76C(11), 1993, pp. 1595-1603
HIGHLY RELIABLE TESTING OF ULSI MEMORIES WITH ON-CHIP VOLTAGE-DOWN CONVERTERS
Authors: TSUKUDE M ARIMOTO K HIDAKA H KONISHI Y HAYASHIKOSHI M SUMA K FUJISHIMA K
Citation: M. Tsukude et al., HIGHLY RELIABLE TESTING OF ULSI MEMORIES WITH ON-CHIP VOLTAGE-DOWN CONVERTERS, IEEE design & test of computers, 10(2), 1993, pp. 6-12
Risultati: 1-14 |