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EVENT-BASED VERIFICATION OF SYNCHRONOUS, GLOBALLY CONTROLLED, LOGIC DESIGNS AGAINST SIGNAL FLOW-GRAPHS
Authors:
VANAELTEN FV ALLEN J DEVADAS S
Citation:
Fv. Vanaelten et al., EVENT-BASED VERIFICATION OF SYNCHRONOUS, GLOBALLY CONTROLLED, LOGIC DESIGNS AGAINST SIGNAL FLOW-GRAPHS, IEEE transactions on computer-aided design of integrated circuits and systems, 13(1), 1994, pp. 122-134
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