Authors: Takahashi, O Dhong, SH Ohkubo, M Onishi, S Dennard, RH Hannon, R Crowder, S Iyer, SS Wordeman, MR Davari, B Weinberger, WB Aoki, N

Citation: O. Takahashi et al., 1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro, IEEE J SOLI, 35(11), 2000, pp. 1673-1679