A BUS-MONITORING MODEL FOR MPEG VIDEO DECODER DESIGN

The variety of macroblock types and variable-length codes has increase d the difficulty in predicting memory accesses and bus utilization pat tern for accessing compressed data or pixels to/from external RAMs dur ing MPEG video decoding process. In this paper, we present a model and a simulator to aid MPEG decoder design by providing useful statistics related to bus utilization and waiting cycles. The model explores MPE G decoder architecture and data nature; it provides results to analyze bus bandwidth and determine proper sizes of decoder I/O buffers conne cted to the bus. Simulation is performed to test out different bus arb itration schemes for MP@ML data in MPEG-2 decoding.