A DISPLAY PROCESSOR CONFORMING TO ALL DTV FORMATS WITH 188-TAP FIR FILTERS AND 284 KB FIFO MEMORIES

To achieve a single chip solution for st display processor conforming to all DTV formats, various hardwired approaches such as the Write End Toggle Signal (WETS) Based Design Technique and Dynamic Voltage Sensi ng FIFO Architecture have been developed. As a result, all functions i ncluding macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chi p. The display processor has a total memory capacity of 284 Kb and fil ters with a total of 188 taps in an area of 14.9 mm x 14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal.