A COMPARISON OF BLOCK-MATCHING ALGORITHMS MAPPED TO SYSTOLIC-ARRAY IMPLEMENTATION

This paper presents an evaluation of several well-known block-matching motion estimation algorithms from a system-level very large scale int egration (VLSI) design viewpoint, Because a straightforward block-matc hing algorithm (BMA) demands a very large amount of computing power, m any fast algorithms have been developed, However, these fast algorithm s are often designed to merely reduce arithmetic operations without co nsidering their overall performance in VLSI implementation, In this pa per, three criteria are used to compare various block-matching algorit hms: 1) silicon area, 2) input/output requirement, and 3) image qualit y. A basic systolic array architecture is chosen to implement all the selected algorithms, The purpose of this study is to compare these rep resentative BMA's using the aforementioned criteria. The advantages/di sadvantages of these algorithms in terms of their hardware tradeoff ar e discussed. The methodology and results presented here provide useful guidelines to system designers in selecting a BMA for VLSI implementa tion.