DESIGN OF FAST MOTION ESTIMATION ALGORITHM-BASED ON HARDWARE CONSIDERATION

Most fast block-matching motion estimation (BMME) algorithms are desig ned to minimize the search positions (or checking points) in a given s earch range in order to speed up the computation, In this paper, we in troduce a fast BMME algorithm based on the consideration of hardware i mplementation, We use a one-dimensional (1-D) systolic array as the ba sic computing engine, In order to utilize this engine efficiently, we process several adjacent checking points, called checking vector, simu ltaneously, We propose a checking-vector-based search strategy and sho w that it can achieve a better algorithmic performance and can be very cost-effective in terms of hardware implementation for low bit-rate v ideo applications.