A RECONFIGURABLE BIT-SERIAL VLSI SYSTOLIC ARRAY NEURO-CHIP

A dynamically reconfigurable bit-serial systolic array implemented in 1.2-mu m double-metal P-well CMOS is described. This processor array i s proposed as the central computational unit in the Reconfigurable Sys tolic Array (RSA) neuro-computer and performance estimates suggest tha t a 64 IC system (containing a total of 1024 usable processors) can ac hieve a learning rate of 1134 MCUPS on the NETtalk problem, The archit ecture employs reconfiguration techniques for both fault-tolerance and functionality, and allows a number of neural network models (in both the recall and learning phases) from associative memory networks, supe rvised networks, and unsupervised networks to be supported, (C) 1997 A cademic Press.