USING CAD TOOLS FOR SHORTENING THE DESIGN CYCLE OF HIGH-PERFORMANCE SIGMA-DELTA MODULATORS - A 16-CENTER-DOT-4 BIT, 9-CENTER-DOT-6 KHZ, 1-CENTER-DOT-71 MW SIGMA-DELTA-M IN CMOS 0-CENTER-DOT-7 MU-M TECHNOLOGY

This paper uses a CAD methodology proposed by the authors to design a low-power second-order Sigma Delta M. This modulator has been fabricat ed in a 0.7 mu m CMOS technology to be used as the front-end of an ene rgy-metering mixed-signal ASIC and features 16.4 bit at a digital outp ut rate of 9.6 kHz with a power consumption of 1.71 mW. It yields a va lue of the power(W)/(2(resolution(bit)) x output rate (Hz)) figure whi ch is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable Sigma Delta Ms using CAD method ologies. (C) 1997 by John Wiley & Sons, Ltd.