This article describes measurement and evaluation algorithms that allo
w full load pull tests to be performed while driving transistors autom
atically into desired gain compression and measuring a selection of pa
rameters, such as output power, gain, efficiency, intermodulation, adj
acent-channel power (ACP), DC bins and harmonic loads, as a function o
f input power. The Design Window evaluation software identifies load c
onditions for which a set of design requirements are fulfilled simulta
neously. Examples of measured contours and three-dimensional surface p
lots are included.