A COMPARATIVE-STUDY OF N(+) P JUNCTION FORMATION FOR DEEP-SUBMICRON ELEVATED SOURCE/DRAIN METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS/

Ultrashallow elevated n(+)/p junctions (similar to 75 nm) incorporatin g selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (similar to 100 nm) were deposited on exposed diffu sion areas in an Advanced Semiconductor Material Epsilon I system spec ifically designed for low thermal budget single-wafer processing. Shal low junctions (similar to 75 nm) were formed by ion implantation (As, 4 x 10(15)/cm(2), 80 keV) into undoped epi layers and out-diffusion in to the underlying substrate. Alternatively, an ion implanted (As, 4 x 10(15)/cm(2), 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10(15)/cm(3), 15 keV) before th e epi deposition All junctions were annealed at 950 degrees C for 10 s . Nonsilicided elevated junctions and conventional nonelevated (As, 1. 5 x 10(15)/cm(2), 15 keV) ones displayed very similar junction charact eristics. Silicided nonelevated ultrashallow junctions, however, showe d large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excelle nt forward characteristics and low reverse leakage current. The differ ence in the reverse leakage characteristics of these two elevated junc tions was attributed to the epi faceting formed at the sidewall edge o f localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating thes e junctions were also fabricated and electrically tested. Both elevate d source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic res istance from contact source/drain junctions.