HIGH-THROUGHPUT, LOW-MEMORY APPLICATIONS ON THE PICA ARCHITECTURE

This paper describes Pica, a fine-grain, message-passing architecture designed to efficiently support high-throughput, low-memory parallel a pplications, such as image processing, object recognition, and data co mpression. By specializing the processor and reducing local memory (4, 096 36-bit words), multiple nodes can be implemented on a single chip. This allows high-performance systems for high-throughput applications to be realized at lower cost. The architecture minimizes overhead for basic parallel operations. An operand-addressed context cache and rou nd-robin task manager support fast task swapping. Fixed-sized activati on contexts simplify storage management. Word-tag synchronization bits provide low-cost synchronization. Several applications have been deve loped for this architecture, including thermal relaxation, matrix mult iplication, JPEG image compression, and Positron Emission Tomography i mage reconstruction. These applications have been executed using an in strumented instruction-level simulator. The results of these experimen ts and an evaluation of Pica's architectural features are presented.