INCORPORATING I-DDQ TESTING WITH BIST FOR IMPROVED COVERAGE - AN EXPERIMENTAL-STUDY

In this paper we present an experimental study on the effectiveness of incorporating at-speed I-DDQ testing with traditional BIST for improv ed test coverage. The high speed I-DDQ testing is conducted using the differential built-in on-chip current sensor (BICS) that we have recen tly developed. Two test chips were designed and fabricated implementin g a CMOS version of the 74181 ALU chip. In copies of this circuit we i ncluded the capability of activating 45 different ''realistic'' CMOS f aults: inter-and intra-layer shorts and opens. We examine the fault co verage of both Boolean (voltage) testing and I-DDQ testing for these r ealistic faults. An interesting finding of our study is that I-DDQ tes ting also detected several of the open faults. Moreover, these include precisely those open faults for which two pattern voltage tests can g et invalidated because of transient switching states. Our results show that combining both Boolean and current testing does enhance test cov erage in a BIST environment.