A VHDL-BASED APPROACH FOR POWER ESTIMATION OF EMBEDDED SYSTEMS

Power dissipation has become one of the main constraints during the de sign of embedded systems and VLSI circuits in the recent years, due to continuous increase of the integration level and the operating freque ncy. The aim of this paper is to present an innovative conceptual fram ework suitable for achieving accurate and efficient estimation of powe r dissipation for embedded systems described in VHDL at the behavioral and Register-Transfer levels. The goal is to provide the designer wit h the capability of analyzing and comparing different solutions in the architectural design space before the synthesis. The analytical power model is hierarchical, considering the different parts of the target system architecture, mainly the data-path, the memory, the control log ic and the embedded core processor. Experimental results are obtained by applying the proposed power model to benchmark circuits.