AN EFFICIENT FPGA TECHNOLOGY MAPPING TIGHTLY COUPLED WITH LOGIC MINIMIZATION

The FPGA logic synthesis consists of logic minimization step and techn ology mapping step. These two steps are usually performed separately t o reduce the complexity of the problem. Conventional logic minimizatio n methods try to minimize the number of literals of a given Boolean ne twork, while FPGA technology mapping techniques attempt to minimize th e number of basic blocks. However, minimizing the number of literals, which is target architecture-independent feature, does not always lead to minimization of basic block count, which is a FPGA architecture sp ecific feature. Therefore, most of the existing technology mapping sys tems take into account reorganization of its input circuits to get bet ter mapping results. Such a loosely coupled logic synthesis paradigm m ay cause difficulties in finding the optimal solution. In this paper, we propose a new logic synthesis approach where logic minimization and technology mapping steps are performed tightly coupled. Our system ta kes into account FPGA specific features in logic minimization step and thus our technology mapping step does not need to resynthesize the Bo olean network. We formulate the technology mapping problem as a graph covering problem. Such formulation provides more global view to optima lity and supports versatile cost functions. In addition, a fast and ex act library management technique is devised for efficient FPGA cell ma tching which is one of the most frequently used operations in the FPGA logic synthesis. To demonstrate the efficiency of our approach, we ap plied our system to MCNC benchmarks and compared the results with thos e of the existing systems. The experimental results show that our appr oach is better than any of the existing systems in terms of area and d elay.