A VARIABLE PARTITIONING ALGORITHM OF BDD FOR FPGA TECHNOLOGY MAPPING

Field Programmable Gate Arrays (FPGA's) are important devices for rapi d system prototyping. Roth-Karp decomposition is one of the most popul ar decomposition techniques for Look-Up Table (LUT)-based FPGA technol ogy mapping. In this paper, we propose a novel algorithm based on Bina ry Decision Diagrams (BDD's) for selecting good lambda set variables i n Roth-Karp decomposition to minimize the number of consumed configura ble logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].