A CO-EVALUATION OF THE ARCHITECTURES AND THE CAD-SYSTEM FOR SPEED-ORIENTED FPGAS

This paper presents an FPGA architecture for high-speed systems, such as next-generation B-ISDN telecommunications systems. Such a system re quires an LSI in which an over-10K-gate circuit can be implemented and that has a clock cycle rate of 80 MHz. So far, the FPGA architecture has only been discussed in terms of its circuit structure. In contrast , we consider the circuit structure of the FPGA along with the perform ance of its dedicated CAD system. We evaluate several FPGA logic-eleme nt structures with a technology mapping method. From these experiments , a multiplexor-based logic-element is found to be suitable for implem enting such a high-speed circuit using the BDD-based technology mappin g method. In addition, we examine how to best utilize the characterist ics of the selected logic-cell structure in designing the wiring struc ture. It is found that the multiplexor-based cell can be connected eff iciently in a clustered wiring structure.