ROUTABILITY ANALYSIS OF BIT-SERIAL PIPELINE DATAPATHS

Authors
ISSHIKI T DAI WWM KUNIEDA H
Citation
T. Isshiki et al., ROUTABILITY ANALYSIS OF BIT-SERIAL PIPELINE DATAPATHS, IEICE transactions on fundamentals of electronics, communications and computer science, E80A(10), 1997, pp. 1861-1870
Citations number
15
Categorie Soggetti
Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture","Computer Science Information Systems
Journal title
IEICE transactions on fundamentals of electronics, communications and computer science → ACNP
ISSN journal
09168508
Volume
E80A
Issue
10
Year of publication
1997
Pages
1861 - 1870
Database
ISI
SICI code
0916-8508(1997)E80A:10<1861:RAOBPD>2.0.ZU;2-N
Abstract
In this paper, we will show some significant results of the routabilit y analysis of bit-serial pipeline datapath designs based on Rent's rul e[1] and Donath's[10] observation. Our results show that all of the te sted bit-serial benchmarks have Rent exponent of below 0.4, indicating that the average wiring length of the circuit is expected to be indep endent of the circuit size. This study provides some important implica tions on the silicon utilization and time-area efficiency of bit-seria l pipeline circuits on FPGAs and ASICs.