A 2-DIMENSIONAL TRANSISTOR PLACEMENT ALGORITHM FOR CELL SYNTHESIS ANDITS APPLICATION TO STANDARD CELLS

We propose a transistor placement algorithm to generate standard cell layout in a two-dimensional placement style. The algorithm optimizes t he one-dimensional placement in the first stage, folds the large trans istors in the second stage, and optimizes the two-dimensional placemen t in the final stage. We also propose ''cost function'' based on wirin g length, which closely match the cell optimization. This transistor p lacement algorithm has been applied to several standard cells, and dem onstrated the capability to generate a two-dimensional placement that is comparable to manually designed placement.