HARDWARE IMPLEMENTATION OF CMAC NEURAL-NETWORK WITH REDUCED STORAGE REQUIREMENT

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexi ty, However, it suffers from a low storage space utilization rate on w eight memory, In this paper, we propose a direct weight address mappin g approach, which can reduce the required weight memory size with a ut ilization rate near 100%. Based on such an address mapping approach, w e developed a pipeline architecture to efficiently perform the address ing operations, The proposed direct weight address mapping approach al so speeds up the computation for the generation of weight addresses, B esides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.