CIRCUIT TECHNIQUES IN A 266-MHZ MMX-ENABLED PROCESSOR

The AMD-K6 MMX-enabled processor is plug-compatible with the industry- standard Socket 7 and is binary compatible with the existing base of l egacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution, High perfor mance and compact die size are achieved by using self-resetting, self- timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells, The 162 sq, mm die is fabr icated on a 0.35-mu m, five-layer metal process with local interconnec t, It is assembled into a ceramic pin grid array (PGA) using C4 flip-c hip mounting. The processor functions at clock speeds up to 266 MHz.