A 400-MHZ S 390 MICROPROCESSOR

A microprocessor implementing IBM S/390 architecture operates in a 10 + 2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fab ricated in a 0.2-mu m L-eff CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm x 17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and meas ured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IU's), two fixed point units (FXU's), two floa ting point units (FPU's), a buffer control element (BCE) with a unifie d 64-KB L1 cache, and a register unit (RU). The microprocessor dispatc hes one instruction per cycle, The dual-instruction, fixed, and floati ng point units are used to check each other to increase reliability an d not for improved performance, A phase-locked-loop (PLL) provides a p rocessor clock that runs at 2x the system bus frequency, High-frequenc y operation was achieved through careful static circuit design and tim ing optimization, along with limited use of dynamic circuits for highl y critical functions, and several different clocking/latching strategi es for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnar ound time. Extensive use of self-resetting CMOS (SRCMOS) circuits in t he on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz op eration.