A 1-V 46-NS 16-MB SOI-DRAM WITH BODY CONTROL TECHNIQUE

Citation
K. Shimomura et al., A 1-V 46-NS 16-MB SOI-DRAM WITH BODY CONTROL TECHNIQUE, IEEE journal of solid-state circuits, 32(11), 1997, pp. 1712-1720
Citations number
14
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00189200
Volume
32
Issue
11
Year of publication
1997
Pages
1712 - 1720
Database
ISI
SICI code
0018-9200(1997)32:11<1712:A141SW>2.0.ZU;2-#
Abstract
A low-voltage high-speed 16-Mb SOI-DRAM has been developed using a 0.5 -mu m CMOS/SIMOX technology, A newly introduced ''FD-PD mode switching '' transistor dynamically switches its operation mode between fully de pleted (FD) and partially depleted (PD) according to the body bias vol tage, thus it has both PD-mode large current drivability and FD-mode s mall leakage current, By the body bias control, the transistor operate s as if it has an S-factor of 30 mV/decade. Enabling both high speed a nd low power at a low voltage, 30 mV is only one-half the theoretical value, By utilizing the transistor, we have developed body pulsed sens e amplifier (BPS), body driven equalizer (BDEQ), body current clamper (BCC), and body pulsed transistor logic (BPTL) to achieve 46 ns access time at 1 V power supply with suppressed standby current.