A 1.2 TO 3.3-V WIDE VOLTAGE-RANGE LOW-POWER DRAM WITH A CHARGE-TRANSFER PRESENSING SCHEME/

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation w ith a 1/2V(cc) bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with convention al sensing schemes. Operation over a 1.2- to 3.3-V range is achieved, A nonreset row block control scheme (NRBC) for power-consumption impro vement in data-retention mode is proposed which decreases the charge/d ischarge number of the row block control circuit. By combining CTPS an d NRBC, the data-retention current is reduced by 75%.