Ts. Jung et al., A 3.3-V SINGLE POWER-SUPPLY 16-MB NONVOLATILE VIRTUAL DRAM USING A NAND FLASH MEMORY TECHNOLOGY, IEEE journal of solid-state circuits, 32(11), 1997, pp. 1748-1757
A 3.3-V 16-Mb nonvolatile memory having operation virtually identical
to DRAM with package pin compatibility has been developed, Read and wr
ite operations are fully DRAM compatible except for a longer RAS prech
arge time after write, Fast random access time of 63 ns with the NAND
hash memory cell is achieved by using a hierarchical row decoder schem
e and a unique folded bit-line architecture which also allows bit-by-b
it program verify and inhibit operation, Fast page mode with a column
address access time of 21 ns is achieved by sensing and latching 4k ce
lls simultaneously, To allow byte alterability, non-volatile restore o
peration with self-contained erase is developed, Self-contained erase
is word-line based, and increased cell disturb due to the word-line ba
sed erase is relaxed by adding a boosted bit-line scheme to a conventi
onal self-boosting technique, The device is fabricated in a 0.5-mu m t
riple-well, p-substrate CMOS process using two-metal and three-poly in
terconnect layers, A resulting die size is 86.6 mm(2), and the effecti
ve cell size including the overhead of string select transistors is 2.
0 mu m(2).