A 500-MHZ 4-MB CMOS PIPELINE-BURST CACHE SRAM WITH POINT-TO-POINT NOISE-REDUCTION CODING I O/

A 32-b 500-MHz 4-1-1-1 operation 4-Mb pipeline burst cache SRAM has be en developed, In order to achieve both high bandwidth operation and sh ort latency operation, me developed the following technologies: 1) a p refetched pipeline-burst scheme with double late-write buffers, 2) gat e size reduction and a bit-line equalization by source resetting, 3) p oint-to-point bidirectional coding I/O's to reduce bus noise and power consumption, and 4) a three-level metal 0.25-mu m CMOS process techno logy with six transistor memory cells.