A MATHEMATICAL BASIS FOR POWER-REDUCTION IN DIGITAL VLSI SYSTEMS

Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: 1) derive lower bounds on th e power dissipation in digital systems; and 2) unify existing power-re duction techniques under a common framework. The proposed basis is der ived from information-theoretic arguments. In particular, a digital si gnal processing algorithm is viewed as a process of information transf er with an inherent information transfer rate requirement of R bits/s. Architectures implementing a given algorithm are equivalent to commun ication networks each with a certain capacity C (also in bits/s), The absolute lower bound on the power dissipation for any given architectu re is then obtained by minimizing the signal power such that its chann el capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic l ower bounds are calculated. The usefulness of the proposed theory is d emonstrated via numerical calculations of lower bounds on power dissip ation for simple static CMOS circuits. Furthermore, a common basis for some of the known power-reduction techniques such as parallel process ing, pipelining and adiabatic logic is also provided.