GENERATION OF CMOS VOLTAGE-CONTROLLED FLOATING RESISTORS

A new generation method to implement CMOS floating resistors is presen ted. The generation method depends on the linearization of the differe ntial current of two matched NMOS transistors in two alternative confi gurations. The CMOS floating resistors implemented are based on using MOS transistors operating in the saturation region with their sources connected to their substrates. New CMOS floating resistors using the p roposed design method are given. The magnitude of each of the proposed CMOS floating resistors is tuned by a control voltage. PSpice simulat ion results of the new proposed CMOS floating resistors indicating the linearity range are also given. (C) 1997 Elsevier Science Ltd.