NONVOLATILE MEMORY OPERATIONS OF METAL-FERROELECTRIC-INSULATOR-SEMICONDUCTOR (MFIS) FETS USING PLZT STO/SI(100) STRUCTURES/

We report fabrication and characterization of p-channel metal-ferroele ctric-insulator-semiconductor (MFIS-)FET's using the PLZT/STO/Si(100) structures and demonstrate nonvolatile memory operations of the MFISFE T's. It is found that I-D-V-G characteristics of PLZT/STO/Si MFIS-FET' s show a hysteresis loop due to the ferroelectric nature of the PLZT f ilm. It is also demonstrated that the I-D can be controlled by the ''w rite'' pulse, which was applied before the measurements, even at the s ame ''read'' gate voltage.