THE DELAY VERNIER PATTERN GENERATION TECHNIQUE

The authors describe a new technique for generating an arbitrary digit al data stream with very fine timing resolution, Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference :between two pro pagation delays rather than by an absolute delay, Because this differe nce can be made very small, the circuit, called the delay vernier gene rator, can achieve unprecedented timing resolution in a particular cir cuit technology, Also, this very precise timing is obtained without re quiring an extremely high speed clock, The generator architecture incl udes delay-locked loop calibration mechanisms to compensate for proces s and temperature variations, A prototype chip was fabricated in a 1.2 -mu m CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably.