NOISE MARGIN ENHANCEMENT IN GAAS ROMS USING CURRENT-MODE LOGIC

Two different techniques that allow the implementation of embedded ROM 's using a conventional GaAs MESFET technology are presented, The firs t approach is based on a novel circuit structure named low leakage cur rent FET circuit (L2FC), which reduces significantly subthreshold curr ents. The second approach is based on pseudo current mode logic (PCML) which is by far the best choice in terms of noise margin levels. This characteristic is found to be the key factor when implementing GaAs R OM's because of its degradation as the number of word lines is increas ed, A 5-Kb ROM and a 2-Kb ROM were designed giving delays in the order of 2 ns and less than 1 ns, respectively, The results demonstrate the effectiveness of these techniques and their significance toward impro ving the noise margin.