METHODOLOGY FOR ENSURING HIGH-RELIABILITY OF VLSI SYSTEMS

As the complexity and density of VLSI systems increase, the logical te st of systems based on stuck-at fault model is not sufficient to guara ntee the high reliability of the system. Recently, a new test approach based on current monitoring, called I-ddq test, becomes very importan t since it can overcome limitations of the conventional logic test. In this work, intra-gate bridge fault is defined and analyzed, and a the orem for full detection of the intra-gate bridge faults is presented. The proposed algorithm can be used effectively for testing highly reli able systems such as ATM switches and electronic equipments of automob iles and airplanes.