J. Riera et al., DERIVING COST-FUNCTIONS FROM CELL LIBRARIES AND REAL ICS TO ALLOW REAL AREA-POWER-DELAY TRADE-OFF IN EARLY STAGES OF LOGIC SYNTHESIS, Journal of systems architecture, 43(1-5), 1997, pp. 119-122
To allow real performance-driven logic synthesis, area, power and dela
y trade-off should be considered from the very early stages of the syn
thesis process. Accurate models must be provided for area occupation,
delay, and power dissipation. Moreover, the model parameters should be
available during all stages of logic synthesis. In this paper we pres
ent the models and derive cost functions to calculate their parameters
. At the early stages of logic synthesis, generic cell library informa
tion and statistical data extracted from real integrated circuits (IC)
are used to calculate the model parameters. As the synthesis process
progress, technology dependent information becomes available and the m
odel parameters are gradually refined.