AN ASYNCHRONOUS CELL LIBRARY FOR SELF-TIMED SYSTEM DESIGNS

The performance of synchronous VLSI system is limited by the speed of the global clock which is further constrained by the clock skew. Self- timed design technique, based on the Muller model, improves performanc e by eliminating the global clock. In order to prevent hazard, a self- timed system should satisfy certain assumptions and timing constraints , therefore special cells are required. The novel Self-timed Cell Libr ary is designed for 1.2 mu m CMOS technology which contains Muller C-e lements, DCVSL circuits, latches and delay elements. It is very useful because: (1) It avoids any possible violations of the assumptions and timing constraints since all cells are custom designed; (2) It provid es a fast and reliable model for self-timed system verification using either SPICE simulator or Verilog(R) simulator; (3) It is flexible sin ce it is compatible with an existing Standard Cell Library. In this pa per, the library is described. Moreover, the simulated and measured ce ll characteristics are compared. Using the library, two [1 x 8] x [8 x 1] matrix multipliers employing (1) DCVSL technique, and (2) micropip eline technique have been implemented as design examples and the resul ts are compared. In addition, this paper also demonstrates the benefit s of custom-layouted C-elements and a new way to realize delay element for micropipeline. The last but not least, two new HCCs are also prop osed.