STATECHART METHODOLOGY FOR THE DESIGN, VALIDATION AND SYNTHESIS OF LARGE-SCALE ASYNCHRONOUS SYSTEMS

We apply a novel methodology, based on statecharts, to the design of l arge scale asynchronous systems. The design is specified at multiple l evels, simulated, animated, and compiled into synthesizable VHDL code by using the Express V-HDL CAD tool. We add a validation sub-system to check correct operation. Express V-HDL is originally synchronous, but we employ it for asynchronous design by avoiding any design dependenc e on the clock, and simulating with fast clock and on-line delays. The tool is demonstrated through a simple FSM. The synthesized synchronou s circuit can be converted into an asynchronous one. Some results of a post-synthesis conversion example are given.